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The EMRIC project is divided in five work packages which deals with the main research objectives:
The scientific coordinator of the project is Sonia Ben Dhia.
Technology selection is a fundamental requirement for system design, especially for long life applications (eg. aeronautics and space industry). Requirements for high electronic performances, long term functions (until end of use), optimized reliability, low cost, less and less weight are key challenges. The demand for increased warranties and severe liabilities of product failures is also becoming a concern of automotive and consumer industry. This growing impact combined with the many unresolved questions of the nano-electronics technology reliability stresses the urgent need for a consistent strategy for dealing with the Long Term Reliability. One of the major challenges will be to ensure electromagnetic behavior until component wear-out.
In this context, WP1 aims at identifying the nanoscale technology issues in term of reliability and EMC. In another way, the WP1 should address the questions of electromagnetic robustness warranties during component life time. Moreover, as all of the studies and results obtained in EMRIC should match the actual industrial context, the industrial requirements of system and circuit concerning EMC and reliability have to be known. This work package aims at:
There is a growing demand for high- performance, reliable and safe electronic devices , whatever the applications are. Long term reliability of future electronic components should be calculable. Innovative methodologies to estimate the reliability level of the end-product embedding nano-scale technologies taking into account the different mission profiles have to be developed . New research project shall offer to the European high-end industry a smarter use of more effective and competitive qualified (for long term usage) electronic systems. Standards related to reliability of ICs, as AECQ100 defines the minimum stress test driven qualification requirements and references test conditions for qualification of integrated circuits (ICs) to ensure a certain level of quality and reliability in the application . EMC qualification phases are systematically realized on burn-in components in parallel with reliability tests so that EMC is only tested at the beginning of the device lifetime. Electrical reliability tests (EMC, ESD, self heating, abnormal supply voltage ...) and endurance tests (heat/cold, wetness, vibration, chemical, durability ...) are always made separately.
In this work package a new EMR component qualification methodology will be developed to merge EMC and reliability tests to give attention to the environment of the device and to the impact of natural aging (e.g. increased of leakages). The EMR qualification procedure will be evaluated on few case studies during the 4 years project
The expected results of this work package are:
For several decades, reliability has been used to be handled empirically. Failure rates forecasts are based on statistical and empirical approaches (accelerated ageing tests performed on a large number of components, extraction of empirical parameters and assessment of the mean time to failure), which are not related to the actual degradation mechanisms. Even if these methods are not very accurate, they gave satisfying results since device lifetimes were longer than the required service lives. However, with the technology shrink to DSM technologies, IC lifetimes are reduced and these methods reach their limits in term of accurate prediction. Therefore IC manufacturers cannot guarantee a sufficient reliability to achieve the desired performance levels expected in automotive, aerospace or medical industries. That’s why researchers have started developing models and approaches related to the device physics. These approaches improve the insight of the link between device failures and degradation mechanisms, enhance the estimation of device lifetime and allow an optimized design for reliability. The objective of this project is to determine the link between the parasitic emission and susceptibility to radio frequency interferences drifts and the intrinsic IC degradations. In order to validate the hypothesis on the primary causes of EMC drifts, a test chip will be designed. The implemented structures will be characterized before and after accelerated aging in order to provide both information about IC degradation signatures on electrical characteristics and EMC drifts. Besides, innovative on-chip measurement will be tested in this test chip to improve the accuracy of measurement of IC internal RF noise.
The expected results of this work package are:
Responsible of the work-package: Sonia Ben Dhia
ICs must pass more and more severe specifications in order to guarantee a safe operation of final applications. Some design techniques are applied by design teams to reduce parasitic emission and/or susceptibility to radio frequency interference at IC level (e.g. including on-chip capacitance, adding differential structures to I/O, spreading spectrum by adding controlled jitter, …). However, these structures can also be damaged by intrinsic degradation mechanisms so that their efficiency to reduce emission or noise can be strongly affected. Drifts of their characteristics due to ageing are not taken into account by designers and they cannot evaluate a sufficient margin to compensate these degradations.
Firstly, this work package aims at measuring the impact of ageing on the efficiency of some usual on-chip protection structures and identifying the most robust techniques . The information given by this study could help designers to select structures that can improve the EMC and the reliability of their designs. Secondly, this work package aims at proposing innovative on-chip EMC protection structures. Their efficiency and robustness will be evaluated. Results will be exploited in different publications and will be transferred to our industrial partner Freescale Semiconductors. A test chip will be designed to test all of these design techniques.
The expected results of this work package are:
Responsible of the work-package: Alexandre Boyer
The evolution of ICs combined with the introduction of severe EMC requirements has forced IC designer to take into account EMC during design cycles. IC manufacturers cannot be content with the traditional strategy which consists in characterizing EMC compliance on a prototype and then adding EMC countermeasures, because the number of redesign iterations necessary to satisfy the EMC specifications becomes too large. Therefore the prediction of performances in term of EMC became a necessity for IC designers these last years, in order to improve the design for EMC and reduce the costs induced by redesign. EMC prediction tools and EMC models have appeared ever since. Our EMC group has been involved in the development of EMC model standard and EMC simulation methodologies and tools for ten years. The same requirements exist for IC reliability. Models and simulation tools has become necessary to predict more accurately the device lifetime prior fabrication and enhance the design for reliability.
In this context, the objective of this work package is to develop a predictive EMR model and simulation approach. This innovative model will reuse the formalisms of EMC standard models (e.g. ICEM, IBIS or ICIM) and will integrate the factor age of the component . This factor will affect some parameters of the models; the evolution will depend on physical laws linked to IC degradation mechanisms. Choice of time dependent elements and associated variation laws will be determined from bibliography on reliability models, results of WP 3 Experimental validation of EMC drifts origins. The EMR model should be able to determine the mean drift of a typical aged component but also the standard deviation of this drift. The proposed model will be validated by the experiments performed on the different test chips developed within the EMRIC project, especially on the second test chip. Different validation structures will be implemented in this second test chip. The proposed model will have to be compatible with standard simulation tools (SPICE or VHDL-AMS based simulation tools). In parallel to the development of an EMR model, an EMC simulation flow integrating the aging parameter will be developed. At the end of the project, this flow will be integrated in the IC-EMC simulation platform developed in our laboratory. Moreover, a proposal of update of standard EMC model (as ICEM and ICIM) to take into account aging effects will be sent to the French standardization committee in charge of EMC aspects UTE.
The expected results of this work package are: