Project presentation

Context

With the continuous trend towards nanoscale technology and increased integration of complex electronic functions in embedded systems, ensuring the electromagnetic compatibility (EMC) of electronic systems is a great challenge. In the past 10 years, concerns about electromagnetic compatibility have risen in importance as low emissions and high immunity to interferences have emerged as key differentiators in overall IC performance. Advances in process integration, higher switching speeds, and more complex circuits tend to increase the amount of parasitic emissions generated by ICs. Reduced supply voltages and an increased number of interfaces tend to decrease the immunity to radio-frequency interference. EMC has become a major cause of IC redesign, mainly due to inadequate design methods and lack of expertise in parasitic noise reduction and immunity improvement.
Introducing new high performance electronic modules in critical applications (such as automotive and aeronautic) forces system manufacturers to optimize system reliability and reduce time to market delivery and manufacturing costs. This trend has triggered off an increasing demand for conclusive statements about future lifetime and function of the product already at the design stage, ranging from electro-magnetic effects (EMC/RF) to thermal management issues and thermo-mechanical reliability forecasts. Thereby the boundary conditions imposed by critical system applications such as higher environmental temperatures, a broad spectrum of vibrations as well as the general trend to smaller structures and interconnects along with a higher power density have to be taken into account. In this context, a new request from electronic equipment suppliers aiming at ensuring the electromagnetic robustness (EMR) of embedded systems appeared recently.

Scientific problematic

The technological evolution of integrated circuits has two consequences:

• a drastic reduction of reliability due to an acceleration of intrinsic degradations, which can modify characteristics of circuits at early stage of their lifetime
• a higher level of difficulty to comply with EMC requirements

In this context, ensuring electromagnetic compatibility for the full lifetime of an electronic circuit / system is a real challenge. Numerous publications have shown that prematurate intrinsic degradations can affect seriously analog and digital circuit performances, without generating any fatal breakdowns. If IC performances are affected by aging, it could also modify both the parasitic emission level and the sensitivity to electromagnetic interferences, and reduce the safety level of electronic systems.

Currently, aging impact on EMC is not taken into account in product qualification stages and no research works have been leaded to clarify its real impact. The EMRIC project aims at answering to the following issue: How ensuring the electromagnetic compatibility of integrated circuits which get older sooner ?

Objectives

The project EMRIC aims at:

• highlighting the EMC level (emission and susceptibility) drifts induced by natural aging of integrated circuits, especially those designed in deep submicron and nanometric technologies
• clarifying the links between the intrinsic wearout mechanisms induced by natural aging and the EMC level drifts
• predicting the EMC level drifts due to natural aging and introducing the parameter "Age" in modeling/simulation flow dedicated to EMC of ICs
• evaluating the robustness to natural aging of emission and susceptibility reduction techniques

The objectives of this project can interest both IC designers and critical system manufacturers. On the one hand, this project aims at integrating EMR concerns at different steps of an IC conception cycle. Using EMC robust design guidelines, integrating EMR models to simulation flow and developing EMR qualification procedures will help IC designer to ensure that EMC levels specify at the beginning of IC lifetime would remain within forecast margins during all the expected lifetime. On the other hand, the EMRIC project will provide EMR qualification test procedures and simulation methodologies to IC end users in order to give realistic and efficient EMR requirements to their IC providers.

Expected results

At the end of the EMRIC project, several results could be delivered to the different partners of the team:

• a new standard proposal for an EMR qualification procedure aiming at characterizing EMC drifts at IC level after aging
• an update of current standard models for EMC of ICs (e.g. ICEM, ICIM, IBIS) for EMR analysis
• a simulation tool dedicated to an accurate prediction of the deviation of emission and susceptibility levels for a given aging
• an innovative on-chip sensor, used to measure directly within the circuit the intrinsic degradation consequences on EMC
• a proposition of time insensitive EMC protection structures and EMR oriented design guidelines